From 5eae81038dd11b0b42333eed6200e4b77634e21c Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Fri, 2 Mar 2018 17:29:17 -0800
Subject: [PATCH] SimJTAG: make the reset/init connectivity more flexible. This
 is because you may want to seperate the two

---
 src/main/scala/devices/debug/Periphery.scala | 11 +++++------
 vsrc/SimJTAG.v                               |  8 ++++++--
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala
index 2496b15d..bcd2afe6 100644
--- a/src/main/scala/devices/debug/Periphery.scala
+++ b/src/main/scala/devices/debug/Periphery.scala
@@ -50,7 +50,8 @@ trait HasPeripheryDebugBundle {
     }
     debug.systemjtag.foreach { sj =>
       //val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
-      val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, sj.reset, c, r, out)
+      val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
+      sj.reset := r
       sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
     }
     debug.psd.foreach { _ <> psd }
@@ -123,15 +124,14 @@ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam
     val exit = UInt(OUTPUT, 32)
   }
 
-  def connect(dutio: JTAGIO, jtag_reset: Bool, tbclock: Clock, tbreset: Bool, tbsuccess: Bool) = {
+  def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
     dutio <> io.jtag
-    jtag_reset := tbreset
 
     io.clock := tbclock
     io.reset := tbreset
 
     io.enable    := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
-    io.init_done := ~tbreset
+    io.init_done := init_done
 
     // Success is determined by the gdbserver
     // which is controlling this simulation.
@@ -152,11 +152,10 @@ class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Paramet
     val init_done = Bool(INPUT)
   }
 
-  def connect(dutio: JTAGIO, jtag_reset: Bool, tbreset: Bool, tbsuccess: Bool) = {
+  def connect(dutio: JTAGIO, tbreset: Bool, tbsuccess: Bool) = {
     dutio <> io.jtag
 
     dutio.TRSTn.foreach{ _:= false.B}
-    jtag_reset := tbreset
 
     io.enable    := ~tbreset
     io.init_done := ~tbreset
diff --git a/vsrc/SimJTAG.v b/vsrc/SimJTAG.v
index 385af3c2..e7aca0af 100644
--- a/vsrc/SimJTAG.v
+++ b/vsrc/SimJTAG.v
@@ -48,6 +48,8 @@ module SimJTAG #(
    bit          __jtag_TDI;
    bit          __jtag_TRSTn;
    int          __exit;
+
+   reg          init_done_sticky;
    
    assign #0.1 jtag_TCK   = __jtag_TCK;
    assign #0.1 jtag_TMS   = __jtag_TMS;
@@ -61,8 +63,10 @@ module SimJTAG #(
       if (reset || r_reset) begin
          __exit = 0;
          tickCounterReg <= TICK_DELAY;
+         init_done_sticky <= 1/b0;
       end else begin
-         if (enable && init_done) begin
+         init_done_sticky <= init_done | init_done_sticky;
+         if (enable && init_done_sticky) begin
             tickCounterReg <= tickCounterNxt;
             if (tickCounterReg == 0) begin
                __exit = jtag_tick(
@@ -72,7 +76,7 @@ module SimJTAG #(
                                   __jtag_TRSTn,
                                   __jtag_TDO);
             end
-         end // if (enable && init_done)
+         end // if (enable && init_done_sticky)
       end // else: !if(reset || r_reset)
    end // always @ (posedge clock)