SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two
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@ -50,7 +50,8 @@ trait HasPeripheryDebugBundle {
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}
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}
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debug.systemjtag.foreach { sj =>
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debug.systemjtag.foreach { sj =>
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//val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
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//val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
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val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, sj.reset, c, r, out)
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val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
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sj.reset := r
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sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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}
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}
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debug.psd.foreach { _ <> psd }
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debug.psd.foreach { _ <> psd }
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@ -123,15 +124,14 @@ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam
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val exit = UInt(OUTPUT, 32)
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val exit = UInt(OUTPUT, 32)
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}
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}
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def connect(dutio: JTAGIO, jtag_reset: Bool, tbclock: Clock, tbreset: Bool, tbsuccess: Bool) = {
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def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
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dutio <> io.jtag
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dutio <> io.jtag
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jtag_reset := tbreset
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io.clock := tbclock
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io.clock := tbclock
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io.reset := tbreset
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io.reset := tbreset
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io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
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io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
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io.init_done := ~tbreset
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io.init_done := init_done
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// Success is determined by the gdbserver
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// Success is determined by the gdbserver
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// which is controlling this simulation.
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// which is controlling this simulation.
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@ -152,11 +152,10 @@ class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Paramet
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val init_done = Bool(INPUT)
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val init_done = Bool(INPUT)
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}
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}
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def connect(dutio: JTAGIO, jtag_reset: Bool, tbreset: Bool, tbsuccess: Bool) = {
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def connect(dutio: JTAGIO, tbreset: Bool, tbsuccess: Bool) = {
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dutio <> io.jtag
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dutio <> io.jtag
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dutio.TRSTn.foreach{ _:= false.B}
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dutio.TRSTn.foreach{ _:= false.B}
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jtag_reset := tbreset
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io.enable := ~tbreset
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io.enable := ~tbreset
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io.init_done := ~tbreset
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io.init_done := ~tbreset
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@ -49,6 +49,8 @@ module SimJTAG #(
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bit __jtag_TRSTn;
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bit __jtag_TRSTn;
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int __exit;
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int __exit;
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reg init_done_sticky;
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assign #0.1 jtag_TCK = __jtag_TCK;
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assign #0.1 jtag_TCK = __jtag_TCK;
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assign #0.1 jtag_TMS = __jtag_TMS;
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assign #0.1 jtag_TMS = __jtag_TMS;
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assign #0.1 jtag_TDI = __jtag_TDI;
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assign #0.1 jtag_TDI = __jtag_TDI;
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@ -61,8 +63,10 @@ module SimJTAG #(
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if (reset || r_reset) begin
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if (reset || r_reset) begin
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__exit = 0;
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__exit = 0;
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tickCounterReg <= TICK_DELAY;
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tickCounterReg <= TICK_DELAY;
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init_done_sticky <= 1/b0;
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end else begin
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end else begin
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if (enable && init_done) begin
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init_done_sticky <= init_done | init_done_sticky;
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if (enable && init_done_sticky) begin
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tickCounterReg <= tickCounterNxt;
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tickCounterReg <= tickCounterNxt;
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if (tickCounterReg == 0) begin
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if (tickCounterReg == 0) begin
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__exit = jtag_tick(
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__exit = jtag_tick(
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@ -72,7 +76,7 @@ module SimJTAG #(
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__jtag_TRSTn,
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__jtag_TRSTn,
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__jtag_TDO);
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__jtag_TDO);
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end
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end
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end // if (enable && init_done)
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end // if (enable && init_done_sticky)
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end // else: !if(reset || r_reset)
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end // else: !if(reset || r_reset)
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end // always @ (posedge clock)
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end // always @ (posedge clock)
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