riscv/rocket-chip
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SimJTAG: make the reset/init connectivity more flexible. This is because you may want to seperate the two

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This commit is contained in:
Megan Wachs
2018-03-02 17:29:17 -08:00
parent 95294bbdcb
commit 5eae81038d
2 changed files with 11 additions and 8 deletions
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11
src/main/scala/devices/debug/Periphery.scala
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@@ -50,7 +50,8 @@ trait HasPeripheryDebugBundle {
}
debug.systemjtag.foreach { sj =>
//val jtag = Module(new JTAGVPI(tckHalfPeriod = tckHalfPeriod, cmdDelay = cmdDelay)).connect(sj.jtag, sj.reset, r, out)
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, sj.reset, c, r, out)
val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out)
sj.reset := r
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
}
debug.psd.foreach { _ <> psd }
@@ -123,15 +124,14 @@ class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam
val exit = UInt(OUTPUT, 32)
}
def connect(dutio: JTAGIO, jtag_reset: Bool, tbclock: Clock, tbreset: Bool, tbsuccess: Bool) = {
def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = {
dutio <> io.jtag
jtag_reset := tbreset
io.clock := tbclock
io.reset := tbreset
io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.")
io.init_done := ~tbreset
io.init_done := init_done
// Success is determined by the gdbserver
// which is controlling this simulation.
@@ -152,11 +152,10 @@ class JTAGVPI(tckHalfPeriod: Int = 2, cmdDelay: Int = 2)(implicit val p: Paramet
val init_done = Bool(INPUT)
}
def connect(dutio: JTAGIO, jtag_reset: Bool, tbreset: Bool, tbsuccess: Bool) = {
def connect(dutio: JTAGIO, tbreset: Bool, tbsuccess: Bool) = {
dutio <> io.jtag
dutio.TRSTn.foreach{ _:= false.B}
jtag_reset := tbreset
io.enable := ~tbreset
io.init_done := ~tbreset