riscv/rocket-chip
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use address map instead of MMIOBase

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This commit is contained in:
Howard Mao 2016-04-21 15:38:43 -07:00
parent 82cacfbc5e
commit 5e793427eb
1 changed files with 3 additions and 3 deletions
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6
groundtest/src/main/scala/regression.scala
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@ -2,7 +2,7 @@ package groundtest
import Chisel._ import Chisel._
import uncore._ import uncore._
import junctions.{MMIOBase, ParameterizedBundle} import junctions.{ParameterizedBundle, HasAddrMapParameters}
import rocket.HellaCacheIO import rocket.HellaCacheIO
import cde.{Parameters, Field} import cde.{Parameters, Field}
@ -14,7 +14,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
} }
abstract class Regression(implicit val p: Parameters) abstract class Regression(implicit val p: Parameters)
extends Module with HasTileLinkParameters { extends Module with HasTileLinkParameters with HasAddrMapParameters {
val io = new RegressionIO val io = new RegressionIO
} }
@ -49,7 +49,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true) io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(p(MMIOBase)) io.cache.req.bits.addr := UInt(addrMap("conf:devicetree").start)
io.cache.req.bits.typ := MT_W io.cache.req.bits.typ := MT_W
io.cache.req.bits.cmd := M_XRD io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0) io.cache.req.bits.tag := UInt(0)