From 5e793427ebf8e427c048c3c296cedefeb40072c4 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 21 Apr 2016 15:38:43 -0700
Subject: [PATCH] use address map instead of MMIOBase

---
 groundtest/src/main/scala/regression.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/groundtest/src/main/scala/regression.scala b/groundtest/src/main/scala/regression.scala
index fb3f21bd..25bd462f 100644
--- a/groundtest/src/main/scala/regression.scala
+++ b/groundtest/src/main/scala/regression.scala
@@ -2,7 +2,7 @@ package groundtest
 
 import Chisel._
 import uncore._
-import junctions.{MMIOBase, ParameterizedBundle}
+import junctions.{ParameterizedBundle, HasAddrMapParameters}
 import rocket.HellaCacheIO
 import cde.{Parameters, Field}
 
@@ -14,7 +14,7 @@ class RegressionIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
 }
 
 abstract class Regression(implicit val p: Parameters)
-    extends Module with HasTileLinkParameters {
+    extends Module with HasTileLinkParameters with HasAddrMapParameters {
   val io = new RegressionIO
 }
 
@@ -49,7 +49,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
   io.mem.grant.ready := Bool(true)
 
   io.cache.req.valid := !get_sent && started
-  io.cache.req.bits.addr := UInt(p(MMIOBase))
+  io.cache.req.bits.addr := UInt(addrMap("conf:devicetree").start)
   io.cache.req.bits.typ := MT_W
   io.cache.req.bits.cmd := M_XRD
   io.cache.req.bits.tag := UInt(0)