move FPGA AXI to HTIF converter into Chisel module

src/main/scala/Fpga.scala

@@ -0,0 +1,27 @@
+package rocketchip
+
+import Chisel._
+import uncore._
+import junctions._
+import cde.Parameters
+
+class ZynqAdapter(implicit val p: Parameters) extends Module
+    with HasTopLevelParameters {
+
+  val adapterParams = p.alterPartial({
+    case NastiKey => NastiParameters(
+      dataBits = 32,
+      addrBits = 32,
+      idBits = 12)
+    case TLId => "L1toL2"
+  })
+
+  val io = new Bundle {
+    val nasti = new NastiIO()(adapterParams).flip
+    val host = new HostIO(htifW).flip
+    val reset = Bool(OUTPUT)
+  }
+
+  val conv = Module(new NastiIOHostIOConverter(htifW)(adapterParams))
+  io <> conv.io
+}

src/main/scala/TestConfigs.scala

@@ -104,6 +104,12 @@ class WithNastiConverterTest extends Config(
       (id: Int, p: Parameters) => Module(new NastiConverterTest()(p))
   })
 
+class WithUnitTest extends Config(
+  (pname, site, here) => pname match {
+    case BuildGroundTest =>
+      (id: Int, p: Parameters) => Module(new UnitTestSuite()(p))
+  })
+
 class GroundTestConfig extends Config(new WithGroundTest ++ new DefaultConfig)
 class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
 class MemtestL2Config extends Config(
@@ -117,6 +123,7 @@ class CacheRegressionTestConfig extends Config(
 class DmaTestConfig extends Config(new WithDmaTest ++ new WithL2Cache ++ new GroundTestConfig)
 class DmaStreamTestConfig extends Config(new WithDmaStreamTest ++ new WithStreamLoopback ++ new WithL2Cache ++ new GroundTestConfig)
 class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
+class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
 
 class FancyMemtestConfig extends Config(
   new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++