diff --git a/fpga-zynq b/fpga-zynq
index bda22dcd..cfc0a61f 160000
--- a/fpga-zynq
+++ b/fpga-zynq
@@ -1 +1 @@
-Subproject commit bda22dcd7edaa984eefa2cc76f72b82a370b9c64
+Subproject commit cfc0a61f3051089f364d9f73f6894734d1e8910b
diff --git a/groundtest b/groundtest
index 88843dbf..c5281b2d 160000
--- a/groundtest
+++ b/groundtest
@@ -1 +1 @@
-Subproject commit 88843dbfe6014d8c1df999669ecd8f985e660ec3
+Subproject commit c5281b2dd2947649cc0e7f642052d703d2d3eeda
diff --git a/junctions b/junctions
index 5e9160b4..5138397a 160000
--- a/junctions
+++ b/junctions
@@ -1 +1 @@
-Subproject commit 5e9160b48a725294c22f4c84072c1a06f9295a29
+Subproject commit 5138397ad2167a8f7c755a42d8640584620119b3
diff --git a/src/main/scala/Fpga.scala b/src/main/scala/Fpga.scala
new file mode 100644
index 00000000..d56d45dc
--- /dev/null
+++ b/src/main/scala/Fpga.scala
@@ -0,0 +1,27 @@
+package rocketchip
+
+import Chisel._
+import uncore._
+import junctions._
+import cde.Parameters
+
+class ZynqAdapter(implicit val p: Parameters) extends Module
+    with HasTopLevelParameters {
+
+  val adapterParams = p.alterPartial({
+    case NastiKey => NastiParameters(
+      dataBits = 32,
+      addrBits = 32,
+      idBits = 12)
+    case TLId => "L1toL2"
+  })
+
+  val io = new Bundle {
+    val nasti = new NastiIO()(adapterParams).flip
+    val host = new HostIO(htifW).flip
+    val reset = Bool(OUTPUT)
+  }
+
+  val conv = Module(new NastiIOHostIOConverter(htifW)(adapterParams))
+  io <> conv.io
+}
diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala
index 85e1b513..fe9f6a81 100644
--- a/src/main/scala/TestConfigs.scala
+++ b/src/main/scala/TestConfigs.scala
@@ -104,6 +104,12 @@ class WithNastiConverterTest extends Config(
       (id: Int, p: Parameters) => Module(new NastiConverterTest()(p))
   })
 
+class WithUnitTest extends Config(
+  (pname, site, here) => pname match {
+    case BuildGroundTest =>
+      (id: Int, p: Parameters) => Module(new UnitTestSuite()(p))
+  })
+
 class GroundTestConfig extends Config(new WithGroundTest ++ new DefaultConfig)
 class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
 class MemtestL2Config extends Config(
@@ -117,6 +123,7 @@ class CacheRegressionTestConfig extends Config(
 class DmaTestConfig extends Config(new WithDmaTest ++ new WithL2Cache ++ new GroundTestConfig)
 class DmaStreamTestConfig extends Config(new WithDmaStreamTest ++ new WithStreamLoopback ++ new WithL2Cache ++ new GroundTestConfig)
 class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
+class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
 
 class FancyMemtestConfig extends Config(
   new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++
diff --git a/uncore b/uncore
index 6e4d5602..09b46007 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 6e4d5602376404836dab6ec6d806437e6886c049
+Subproject commit 09b460078a16ea28c88dafb8520eda828a89b992