riscv/rocket-chip
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Minor Rocket fixes to support fLen != xLen

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This commit is contained in:
Andrew Waterman 2018-02-20 15:42:50 -08:00
parent bd29184e11
commit 5e35015651
4 changed files with 17 additions and 9 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -687,7 +687,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
// AMOs
if (usingRMW) {
val amoalu = Module(new AMOALU(xLen))
// when xLen < coreDataBits (e.g. RV32D), this AMOALU is wider than necessary
val amoalu = Module(new AMOALU(coreDataBits))
amoalu.io.mask := pstore1_mask
amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
amoalu.io.lhs := s2_data_word

4
src/main/scala/rocket/HellaCache.scala
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@ -46,8 +46,8 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParamet
val cacheParams = tileParams.dcache.get
val cfg = cacheParams
def wordBits = xLen // really, xLen max
def wordBytes = wordBits/8
def wordBits = coreDataBits
def wordBytes = coreDataBytes
def wordOffBits = log2Up(wordBytes)
def beatBytes = cacheBlockBytes / cacheDataBeats
def beatWords = beatBytes / wordBytes

8
src/main/scala/rocket/RocketCore.scala
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@ -250,8 +250,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
val dcache_bypass_data =
if (fastLoadByte) io.dmem.resp.bits.data
else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass
if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)
else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)
else wb_reg_wdata
// detect bypass opportunities
@ -527,7 +527,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val wb_wen = wb_valid && wb_ctrl.wxd
val rf_wen = wb_wen || ll_wen
val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data,
val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),
Mux(ll_wen, ll_wdata,
Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
wb_reg_wdata)))
@ -676,7 +676,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
io.dmem.req.bits.phys := Bool(false)
io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
io.dmem.invalidate_lr := wb_xcpt
io.dmem.s1_data.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill((xLen max fLen) / fLen, io.fpu.store_data), mem_reg_rs2))
io.dmem.s1_kill := killm_common || mem_breakpoint
io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common

11
src/main/scala/tile/FPU.scala
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@ -168,6 +168,12 @@ class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val exc = Bits(width = FPConstants.FLAGS_SZ)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(width = FPConstants.RM_SZ)
val typ = Bits(width = 2)
val in1 = Bits(width = xLen)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(width = FPConstants.RM_SZ)
val fmaCmd = Bits(width = 2)
@ -233,6 +239,7 @@ object FType {
}
trait HasFPUParameters {
require(fLen == 32 || fLen == 64)
val fLen: Int
def xLen: Int
val minXLen = 32
@ -390,7 +397,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
val store = ieee(in.in1)
val toint = Wire(init = store)
val intType = Wire(init = tag)
io.out.bits.store := ((0 until nIntTypes).map(i => Fill(1 << (nIntTypes - i - 1), store((minXLen << i) - 1, 0))): Seq[UInt])(tag)
io.out.bits.store := (floatTypes.map(t => Fill(maxType.ieeeWidth / t.ieeeWidth, store(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := Bits(0)
@ -441,7 +448,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
val io = new Bundle {
val in = Valid(new FPInput).flip
val in = Valid(new IntToFPInput).flip
val out = Valid(new FPResult)
}