Minor Rocket fixes to support fLen != xLen
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5e35015651
@ -687,7 +687,8 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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// AMOs
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if (usingRMW) {
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val amoalu = Module(new AMOALU(xLen))
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// when xLen < coreDataBits (e.g. RV32D), this AMOALU is wider than necessary
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val amoalu = Module(new AMOALU(coreDataBits))
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amoalu.io.mask := pstore1_mask
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amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
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amoalu.io.lhs := s2_data_word
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@ -46,8 +46,8 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParamet
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val cacheParams = tileParams.dcache.get
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val cfg = cacheParams
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def wordBits = xLen // really, xLen max
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def wordBytes = wordBits/8
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def wordBits = coreDataBits
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def wordBytes = coreDataBytes
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def wordOffBits = log2Up(wordBytes)
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def beatBytes = cacheBlockBytes / cacheDataBeats
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def beatWords = beatBytes / wordBytes
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@ -250,8 +250,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses)
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val dcache_bypass_data =
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if (fastLoadByte) io.dmem.resp.bits.data
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else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass
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if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0)
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else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0)
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else wb_reg_wdata
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// detect bypass opportunities
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@ -527,7 +527,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val wb_wen = wb_valid && wb_ctrl.wxd
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val rf_wen = wb_wen || ll_wen
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val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr)
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val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data,
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val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0),
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Mux(ll_wen, ll_wdata,
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Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata,
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wb_reg_wdata)))
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@ -676,7 +676,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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io.dmem.req.bits.phys := Bool(false)
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io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out)
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io.dmem.invalidate_lr := wb_xcpt
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io.dmem.s1_data.data := Mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
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io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill((xLen max fLen) / fLen, io.fpu.store_data), mem_reg_rs2))
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io.dmem.s1_kill := killm_common || mem_breakpoint
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io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common
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@ -168,6 +168,12 @@ class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
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val exc = Bits(width = FPConstants.FLAGS_SZ)
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}
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class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
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val rm = Bits(width = FPConstants.RM_SZ)
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val typ = Bits(width = 2)
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val in1 = Bits(width = xLen)
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}
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class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
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val rm = Bits(width = FPConstants.RM_SZ)
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val fmaCmd = Bits(width = 2)
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@ -233,6 +239,7 @@ object FType {
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}
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trait HasFPUParameters {
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require(fLen == 32 || fLen == 64)
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val fLen: Int
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def xLen: Int
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val minXLen = 32
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@ -390,7 +397,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
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val store = ieee(in.in1)
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val toint = Wire(init = store)
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val intType = Wire(init = tag)
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io.out.bits.store := ((0 until nIntTypes).map(i => Fill(1 << (nIntTypes - i - 1), store((minXLen << i) - 1, 0))): Seq[UInt])(tag)
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io.out.bits.store := (floatTypes.map(t => Fill(maxType.ieeeWidth / t.ieeeWidth, store(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
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io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
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io.out.bits.exc := Bits(0)
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@ -441,7 +448,7 @@ class FPToInt(implicit p: Parameters) extends FPUModule()(p) {
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class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) {
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val io = new Bundle {
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val in = Valid(new FPInput).flip
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val in = Valid(new IntToFPInput).flip
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val out = Valid(new FPResult)
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}
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