RegMapper: regmap(...) now takes BYTE addresses

If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.

This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.

src/main/scala/uncore/devices/Prci.scala

@@ -74,14 +74,11 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
    * bff8 mtime lo
    * bffc mtime hi
    */
-  val ipi_base     = 0
-  val timecmp_base = c.timecmpOffset(0) / c.beatBytes
-  val time_base    = c.timeOffset / c.beatBytes
 
-  regmap((
-    RegField.split(makeRegFields(ipi),             ipi_base,     c.beatBytes) ++
-    RegField.split(makeRegFields(timecmp.flatten), timecmp_base, c.beatBytes) ++
-    RegField.split(makeRegFields(time),            time_base,    c.beatBytes)):_*)
+  regmap(
+    0                  -> makeRegFields(ipi),
+    c.timecmpOffset(0) -> makeRegFields(timecmp.flatten),
+    c.timeOffset       -> makeRegFields(time))
 
   def makeRegFields(s: Seq[UInt]) = s.map(r => RegField(regWidth, r))
 }