riscv/rocket-chip
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fix bug in quine mccluskey

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This commit is contained in:
Andrew Waterman 2012-11-05 00:28:25 -08:00
parent e9eca6a95d
commit 5e103054fd
1 changed files with 6 additions and 5 deletions
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11
rocket/src/main/scala/decode.scala
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@ -52,7 +52,7 @@ class Term(val value: BigInt, val mask: BigInt = 0)
{ {
var prime = true var prime = true
def covers(x: Term) = ((value ^ x.value) &~ mask) == 0 def covers(x: Term) = ((value ^ x.value) &~ mask | x.mask &~ mask) == 0
def intersects(x: Term) = ((value ^ x.value) &~ mask &~ x.mask) == 0 def intersects(x: Term) = ((value ^ x.value) &~ mask &~ x.mask) == 0
override def equals(that: Any) = that match { override def equals(that: Any) = that match {
case x: Term => x.value == value && x.mask == mask case x: Term => x.value == value && x.mask == mask
@ -182,14 +182,15 @@ object SimplifyDC
prime.sort(_<_) prime.sort(_<_)
} }
def verify(cover: Seq[Term], minterms: Seq[Term], maxterms: Seq[Term]) = {
assert(minterms.forall(t => cover.exists(_ covers t)))
assert(maxterms.forall(t => !cover.exists(_ intersects t)))
}
def apply(minterms: Seq[Term], maxterms: Seq[Term], bits: Int) = { def apply(minterms: Seq[Term], maxterms: Seq[Term], bits: Int) = {
val prime = getPrimeImplicants(minterms, maxterms, bits) val prime = getPrimeImplicants(minterms, maxterms, bits)
assert(minterms.forall(t => prime.exists(_ covers t)))
val (eprime, prime2, uncovered) = Simplify.getEssentialPrimeImplicants(prime, minterms) val (eprime, prime2, uncovered) = Simplify.getEssentialPrimeImplicants(prime, minterms)
assert(uncovered.forall(t => prime2.exists(_ covers t)))
val cover = eprime ++ Simplify.getCover(prime2, uncovered, bits) val cover = eprime ++ Simplify.getCover(prime2, uncovered, bits)
minterms.foreach(t => assert(cover.exists(_.covers(t)))) // sanity check verify(cover, minterms, maxterms)
maxterms.foreach(t => assert(!cover.exists(_.intersects(t)))) // sanity check
cover cover
} }
} }