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tilelink2 Legacy: uncached TL never needs manager_xact_id

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Wesley W. Terpstra 2016-11-16 12:16:25 -08:00
parent 10e459fedb
commit 5d2e637a4a
1 changed files with 1 additions and 4 deletions
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5
src/main/scala/uncore/tilelink2/Legacy.scala
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@ -47,9 +47,6 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
// TL legacy will not generate PutFull // TL legacy will not generate PutFull
// During conversion from TL Legacy, we won't support Acquire // During conversion from TL Legacy, we won't support Acquire
// Must be able to fit TL2 sink_id into TL legacy
require ((1 << tlManagerXactIdBits) >= edge.manager.endSinkId || !edge.manager.anySupportAcquire)
val out = io.out(0) val out = io.out(0)
out.a.valid := io.legacy.acquire.valid out.a.valid := io.legacy.acquire.valid
out.d.ready := io.legacy.grant .ready out.d.ready := io.legacy.grant .ready
@ -134,7 +131,7 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
TLMessages.HintAck -> Grant.prefetchAckType)) TLMessages.HintAck -> Grant.prefetchAckType))
grant.is_builtin_type := Bool(true) grant.is_builtin_type := Bool(true)
grant.client_xact_id := out.d.bits.source grant.client_xact_id := out.d.bits.source
grant.manager_xact_id := out.d.bits.sink grant.manager_xact_id := UInt(0)
grant.data := out.d.bits.data grant.data := out.d.bits.data
grant.addr_beat := beatCounter grant.addr_beat := beatCounter