diff --git a/src/main/scala/uncore/tilelink2/Legacy.scala b/src/main/scala/uncore/tilelink2/Legacy.scala
index 3fa75774..98ae2ae2 100644
--- a/src/main/scala/uncore/tilelink2/Legacy.scala
+++ b/src/main/scala/uncore/tilelink2/Legacy.scala
@@ -47,9 +47,6 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
     // TL legacy will not generate PutFull
     // During conversion from TL Legacy, we won't support Acquire
 
-    // Must be able to fit TL2 sink_id into TL legacy
-    require ((1 << tlManagerXactIdBits) >= edge.manager.endSinkId || !edge.manager.anySupportAcquire)
-
     val out = io.out(0)
     out.a.valid := io.legacy.acquire.valid
     out.d.ready := io.legacy.grant  .ready
@@ -134,7 +131,7 @@ class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkPa
       TLMessages.HintAck       -> Grant.prefetchAckType))
     grant.is_builtin_type := Bool(true)
     grant.client_xact_id  := out.d.bits.source
-    grant.manager_xact_id := out.d.bits.sink
+    grant.manager_xact_id := UInt(0)
     grant.data            := out.d.bits.data
     grant.addr_beat       := beatCounter