ahb: include a unit test
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36
src/main/scala/uncore/ahb/Test.scala
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36
src/main/scala/uncore/ahb/Test.scala
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@ -0,0 +1,36 @@
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// See LICENSE.SiFive for license details.
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package uncore.ahb
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import Chisel._
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import config._
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import diplomacy._
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import uncore.tilelink2._
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import unittest._
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class RRTest0(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter(address, 0, 32, 0, 4)(
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new AHBRegBundle((), _) with RRTest0Bundle)(
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new AHBRegModule((), _, _) with RRTest0Module)
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class RRTest1(address: BigInt)(implicit p: Parameters) extends AHBRegisterRouter(address, 0, 32, 1, 4, false)(
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new AHBRegBundle((), _) with RRTest1Bundle)(
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new AHBRegModule((), _, _) with RRTest1Module)
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class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
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{
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val fuzz = LazyModule(new TLFuzzer(5000))
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val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
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val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
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model.node := fuzz.node
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ram.node := TLToAHB()(model.node)
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lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
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io.finished := fuzz.module.io.finished
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}
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}
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class AHBBridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
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val dut = Module(LazyModule(new AHBFuzzBridge).module)
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io.finished := dut.io.finished
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}
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@ -32,6 +32,7 @@ class WithUncoreUnitTests extends Config(
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Module(new uncore.devices.TileLinkRAMTest()),
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Module(new uncore.devices.TileLinkRAMTest()),
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Module(new uncore.converters.TileLinkWidthAdapterTest()),
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Module(new uncore.converters.TileLinkWidthAdapterTest()),
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Module(new uncore.tilelink2.TLFuzzRAMTest),
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Module(new uncore.tilelink2.TLFuzzRAMTest),
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Module(new uncore.ahb.AHBBridgeTest),
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Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
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Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
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Module(new uncore.axi4.AXI4FullFuzzRAMTest),
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Module(new uncore.axi4.AXI4FullFuzzRAMTest),
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Module(new uncore.axi4.AXI4BridgeTest)) }
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Module(new uncore.axi4.AXI4BridgeTest)) }
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