riscv/rocket-chip
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Merge pull request #32 from ucb-bar/pr-btb-masking

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separate btb response mask from the frontend mask
This commit is contained in:
Andrew Waterman
2016-03-26 18:15:14 -07:00
parent ed280fb3de f526d380fd
commit 5ce3527b88
2 changed files with 3 additions and 3 deletions
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4
rocket/src/main/scala/btb.scala
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@@ -115,8 +115,8 @@ class RASUpdate(implicit p: Parameters) extends BtbBundle()(p) {
// - "bridx" is the low-order PC bits of the predicted branch (after // - "bridx" is the low-order PC bits of the predicted branch (after
// shifting off the lowest log(inst_bytes) bits off). // shifting off the lowest log(inst_bytes) bits off).
// - "resp.mask" provides a mask of valid instructions (instructions are // - "mask" provides a mask of valid instructions (instructions are
// masked off by the predicted taken branch). // masked off by the predicted taken branch from the BTB).
class BTBResp(implicit p: Parameters) extends BtbBundle()(p) { class BTBResp(implicit p: Parameters) extends BtbBundle()(p) {
val taken = Bool() val taken = Bool()
val mask = Bits(width = fetchWidth) val mask = Bits(width = fetchWidth)

2
rocket/src/main/scala/frontend.scala
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@@ -131,7 +131,7 @@ class Frontend(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePa
val all_ones = UInt((1 << (fetchWidth+1))-1) val all_ones = UInt((1 << (fetchWidth+1))-1)
val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2) val msk_pc = if (fetchWidth == 1) all_ones else all_ones << s2_pc(log2Up(fetchWidth) -1+2,2)
io.cpu.resp.bits.mask := Mux(s2_btb_resp_valid, msk_pc & s2_btb_resp_bits.mask, msk_pc) io.cpu.resp.bits.mask := msk_pc
io.cpu.resp.bits.xcpt_if := s2_xcpt_if io.cpu.resp.bits.xcpt_if := s2_xcpt_if
io.cpu.btb_resp.valid := s2_btb_resp_valid io.cpu.btb_resp.valid := s2_btb_resp_valid