riscv/rocket-chip
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new tilelink arbiter type

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Henry Cook committed 2013-07-09 15:31:46 -07:00
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commit 5c00d0a030
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rocket/src/main/scala/tile.scala
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@@ -40,7 +40,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
val icache = new Frontend()(confIn.icache, lnConf)
val dcache = new HellaCache
val arbiter = new UncachedTileLinkIOArbiter(memPorts, confIn.dcache.co)
val arbiter = new UncachedTileLinkIOArbiterThatAppendsArbiterId(memPorts, confIn.dcache.co)
arbiter.io.in(dcachePortId) <> dcache.io.mem
arbiter.io.in(icachePortId) <> icache.io.mem