riscv/rocket-chip
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rocket: add dts cpu description

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This commit is contained in:
Wesley W. Terpstra
2017-03-01 16:47:10 -08:00
parent cfd367248f
commit 5bd9f18e5b
3 changed files with 69 additions and 8 deletions
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6
src/main/scala/coreplex/RocketTiles.scala
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@ -43,7 +43,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
crossing match {
case Synchronous => {
val tile = LazyModule(new RocketTile(c)(pWithExtra))
val tile = LazyModule(new RocketTile(c, i)(pWithExtra))
val buffer = LazyModule(new TLBuffer)
buffer.node :=* tile.masterNode
l1tol2.node :=* buffer.node
@ -56,7 +56,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
}
case Asynchronous(depth, sync) => {
val wrapper = LazyModule(new AsyncRocketTile(c)(pWithExtra))
val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
val source = LazyModule(new TLAsyncCrossingSource(sync))
sink.node :=* wrapper.masterNode
@ -72,7 +72,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
}
case Rational => {
val wrapper = LazyModule(new RationalRocketTile(c)(pWithExtra))
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
val source = LazyModule(new TLRationalCrossingSource)
sink.node :=* wrapper.masterNode