riscv/rocket-chip
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rename l2FrontendBus as fsb, expose bsb

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Yunsup Lee 2017-03-24 21:37:47 -07:00 committed by Wesley W. Terpstra
parent 996a31364a
commit 5bbb75e078
4 changed files with 10 additions and 4 deletions
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4
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -26,6 +26,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
val mmio = TLOutputNode() val mmio = TLOutputNode()
val mmioInt = IntInputNode() val mmioInt = IntInputNode()
val l2in = TLInputNode() val l2in = TLInputNode()
val l2out = TLOutputNode()
intBar.intnode := mmioInt intBar.intnode := mmioInt
@ -42,6 +43,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
TLWidthWidget(l1tol2_beatBytes)( TLWidthWidget(l1tol2_beatBytes)(
l1tol2.node) l1tol2.node)
l2out :*= l1tol2.node
val root = new Device { val root = new Device {
def describe(resources: ResourceBindings): Description = { def describe(resources: ResourceBindings): Description = {
val width = resources("width").map(_.value) val width = resources("width").map(_.value)
@ -96,6 +99,7 @@ trait CoreplexNetworkBundle extends HasCoreplexParameters {
val mmio = outer.mmio.bundleOut val mmio = outer.mmio.bundleOut
val interrupts = outer.mmioInt.bundleIn val interrupts = outer.mmioInt.bundleIn
val l2in = outer.l2in.bundleIn val l2in = outer.l2in.bundleIn
val l2out = outer.l2out.bundleOut
} }
trait CoreplexNetworkModule extends HasCoreplexParameters { trait CoreplexNetworkModule extends HasCoreplexParameters {

3
src/main/scala/rocketchip/BaseTop.scala
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@ -36,7 +36,8 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH) val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL) val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
val intBus = LazyModule(new IntXbar) // Interrupts val intBus = LazyModule(new IntXbar) // Interrupts
val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2 val fsb = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2
val bsb = LazyModule(new TLBuffer) // Slave devices talking to the backside of the L2
val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
// The peripheryBus hangs off of socBus; // The peripheryBus hangs off of socBus;

4
src/main/scala/rocketchip/Periphery.scala
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@ -214,7 +214,7 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
masters = Seq(AXI4MasterParameters( masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << config.idBits)))))) id = IdRange(0, 1 << config.idBits))))))
l2FrontendBus.node := fsb.node :=
TLSourceShrinker(1 << config.sourceBits)( TLSourceShrinker(1 << config.sourceBits)(
TLWidthWidget(config.beatBytes)( TLWidthWidget(config.beatBytes)(
AXI4ToTL()( AXI4ToTL()(
@ -282,7 +282,7 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
clients = Seq(TLClientParameters( clients = Seq(TLClientParameters(
sourceId = IdRange(0, 1 << config.idBits)))))) sourceId = IdRange(0, 1 << config.idBits))))))
l2FrontendBus.node := fsb.node :=
TLSourceShrinker(1 << config.sourceBits)( TLSourceShrinker(1 << config.sourceBits)(
TLWidthWidget(config.beatBytes)( TLWidthWidget(config.beatBytes)(
l2FrontendTLNode)) l2FrontendTLNode))

3
src/main/scala/rocketchip/RocketPlexMaster.scala
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@ -15,7 +15,8 @@ trait RocketPlexMaster extends HasTopLevelNetworks {
val coreplex = LazyModule(new DefaultCoreplex) val coreplex = LazyModule(new DefaultCoreplex)
coreplex.l2in :=* l2FrontendBus.node coreplex.l2in :=* fsb.node
bsb.node :*= coreplex.l2out
socBus.node := coreplex.mmio socBus.node := coreplex.mmio
coreplex.mmioInt := intBus.intnode coreplex.mmioInt := intBus.intnode