From 5bbb75e078ec8e01d2ff6046ada68654d5f1e788 Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@sifive.com>
Date: Fri, 24 Mar 2017 21:37:47 -0700
Subject: [PATCH] rename l2FrontendBus as fsb, expose bsb

---
 src/main/scala/coreplex/CoreplexNetwork.scala    | 4 ++++
 src/main/scala/rocketchip/BaseTop.scala          | 3 ++-
 src/main/scala/rocketchip/Periphery.scala        | 4 ++--
 src/main/scala/rocketchip/RocketPlexMaster.scala | 3 ++-
 4 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala
index 811620f1..db049848 100644
--- a/src/main/scala/coreplex/CoreplexNetwork.scala
+++ b/src/main/scala/coreplex/CoreplexNetwork.scala
@@ -26,6 +26,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   val mmio = TLOutputNode()
   val mmioInt = IntInputNode()
   val l2in = TLInputNode()
+  val l2out = TLOutputNode()
 
   intBar.intnode := mmioInt
 
@@ -42,6 +43,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
     TLWidthWidget(l1tol2_beatBytes)(
     l1tol2.node)
 
+  l2out :*= l1tol2.node
+
   val root = new Device {
     def describe(resources: ResourceBindings): Description = {
       val width = resources("width").map(_.value)
@@ -96,6 +99,7 @@ trait CoreplexNetworkBundle extends HasCoreplexParameters {
   val mmio = outer.mmio.bundleOut
   val interrupts = outer.mmioInt.bundleIn
   val l2in = outer.l2in.bundleIn
+  val l2out = outer.l2out.bundleOut
 }
 
 trait CoreplexNetworkModule extends HasCoreplexParameters {
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 7e2638d3..d671b8e7 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -36,7 +36,8 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
   val socBus = LazyModule(new TLXbar)          // Wide or unordered-access slave devices (TL-UH)
   val peripheryBus = LazyModule(new TLXbar)    // Narrow and ordered-access slave devices (TL-UL)
   val intBus = LazyModule(new IntXbar)         // Interrupts
-  val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2
+  val fsb = LazyModule(new TLBuffer)           // Master devices talking to the frontside of the L2
+  val bsb = LazyModule(new TLBuffer)           // Slave devices talking to the backside of the L2
   val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
 
   // The peripheryBus hangs off of socBus;
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 4b1776ea..b5b9cc48 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -214,7 +214,7 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
     masters = Seq(AXI4MasterParameters(
       id = IdRange(0, 1 << config.idBits))))))
 
-  l2FrontendBus.node :=
+  fsb.node :=
     TLSourceShrinker(1 << config.sourceBits)(
     TLWidthWidget(config.beatBytes)(
     AXI4ToTL()(
@@ -282,7 +282,7 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
     clients = Seq(TLClientParameters(
       sourceId = IdRange(0, 1 << config.idBits))))))
 
-  l2FrontendBus.node :=
+  fsb.node :=
     TLSourceShrinker(1 << config.sourceBits)(
     TLWidthWidget(config.beatBytes)(
     l2FrontendTLNode))
diff --git a/src/main/scala/rocketchip/RocketPlexMaster.scala b/src/main/scala/rocketchip/RocketPlexMaster.scala
index 8d2bf546..d0a31dd1 100644
--- a/src/main/scala/rocketchip/RocketPlexMaster.scala
+++ b/src/main/scala/rocketchip/RocketPlexMaster.scala
@@ -15,7 +15,8 @@ trait RocketPlexMaster extends HasTopLevelNetworks {
 
   val coreplex = LazyModule(new DefaultCoreplex)
 
-  coreplex.l2in :=* l2FrontendBus.node
+  coreplex.l2in :=* fsb.node
+  bsb.node :*= coreplex.l2out
   socBus.node := coreplex.mmio
   coreplex.mmioInt := intBus.intnode