rename l2FrontendBus as fsb, expose bsb

src/main/scala/rocketchip/BaseTop.scala

@@ -36,7 +36,8 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
   val socBus = LazyModule(new TLXbar)          // Wide or unordered-access slave devices (TL-UH)
   val peripheryBus = LazyModule(new TLXbar)    // Narrow and ordered-access slave devices (TL-UL)
   val intBus = LazyModule(new IntXbar)         // Interrupts
-  val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2
+  val fsb = LazyModule(new TLBuffer)           // Master devices talking to the frontside of the L2
+  val bsb = LazyModule(new TLBuffer)           // Slave devices talking to the backside of the L2
   val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
 
   // The peripheryBus hangs off of socBus;

src/main/scala/rocketchip/Periphery.scala

@@ -214,7 +214,7 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
     masters = Seq(AXI4MasterParameters(
       id = IdRange(0, 1 << config.idBits))))))
 
-  l2FrontendBus.node :=
+  fsb.node :=
     TLSourceShrinker(1 << config.sourceBits)(
     TLWidthWidget(config.beatBytes)(
     AXI4ToTL()(
@@ -282,7 +282,7 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
     clients = Seq(TLClientParameters(
       sourceId = IdRange(0, 1 << config.idBits))))))
 
-  l2FrontendBus.node :=
+  fsb.node :=
     TLSourceShrinker(1 << config.sourceBits)(
     TLWidthWidget(config.beatBytes)(
     l2FrontendTLNode))

src/main/scala/rocketchip/RocketPlexMaster.scala

@@ -15,7 +15,8 @@ trait RocketPlexMaster extends HasTopLevelNetworks {
 
   val coreplex = LazyModule(new DefaultCoreplex)
 
-  coreplex.l2in :=* l2FrontendBus.node
+  coreplex.l2in :=* fsb.node
+  bsb.node :*= coreplex.l2out
   socBus.node := coreplex.mmio
   coreplex.mmioInt := intBus.intnode