riscv/rocket-chip
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rename l2FrontendBus as fsb, expose bsb

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This commit is contained in:
Yunsup Lee
2017-03-24 21:37:47 -07:00
committed by Wesley W. Terpstra
parent 996a31364a
commit 5bbb75e078
4 changed files with 10 additions and 4 deletions
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4
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -26,6 +26,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
val mmio = TLOutputNode()
val mmioInt = IntInputNode()
val l2in = TLInputNode()
val l2out = TLOutputNode()
intBar.intnode := mmioInt
@ -42,6 +43,8 @@ trait CoreplexNetwork extends HasCoreplexParameters {
TLWidthWidget(l1tol2_beatBytes)(
l1tol2.node)
l2out :*= l1tol2.node
val root = new Device {
def describe(resources: ResourceBindings): Description = {
val width = resources("width").map(_.value)
@ -96,6 +99,7 @@ trait CoreplexNetworkBundle extends HasCoreplexParameters {
val mmio = outer.mmio.bundleOut
val interrupts = outer.mmioInt.bundleIn
val l2in = outer.l2in.bundleIn
val l2out = outer.l2out.bundleOut
}
trait CoreplexNetworkModule extends HasCoreplexParameters {