riscv/rocket-chip
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rename internal/external MMIO network to cbus/pbus respectively

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This commit is contained in:
Yunsup Lee
2016-09-21 18:16:04 -07:00
parent 3a809b209f
commit 5bb575ef74
8 changed files with 25 additions and 25 deletions
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4
src/main/scala/rocketchip/Periphery.scala
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@ -204,10 +204,10 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryMasterMMIO
val io: PeripheryMasterMMIOBundle
val mmioNetwork: TileLinkRecursiveInterconnect
val pBus: TileLinkRecursiveInterconnect
val mmio_ports = p(ExtMMIOPorts) map { port =>
TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost")
TileLinkWidthAdapter(pBus.port(port.name), "MMIO_Outermost")
}
val mmio_axi_start = 0