riscv/rocket-chip
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rename internal/external MMIO network to cbus/pbus respectively

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This commit is contained in:
Yunsup Lee
2016-09-21 18:16:04 -07:00
parent 3a809b209f
commit 5bb575ef74
8 changed files with 25 additions and 25 deletions
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8
src/main/scala/rocketchip/BaseTop.scala
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@@ -65,11 +65,11 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
val coreplex = p(BuildCoreplex)(outer.c, p)
val coreplexIO = coreplex.io
val mmioNetwork =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
mmioNetwork.io.in.head <> coreplexIO.master.mmio.get
outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
pBus.io.in.head <> coreplexIO.master.mmio.get
outer.legacy.module.io.legacy <> pBus.port("TL2")
println("Generated Address Map")
for (entry <- p(GlobalAddrMap).flatten) {