riscv/rocket-chip
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rename internal/external MMIO network to cbus/pbus respectively

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This commit is contained in:
Yunsup Lee
2016-09-21 18:16:04 -07:00
parent 3a809b209f
commit 5bb575ef74
8 changed files with 25 additions and 25 deletions
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8
src/main/scala/rocketchip/BaseTop.scala
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@ -65,11 +65,11 @@ abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](
val coreplex = p(BuildCoreplex)(outer.c, p)
val coreplexIO = coreplex.io
val mmioNetwork =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
val pBus =
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:pbus"))(
p.alterPartial({ case TLId => "L2toMMIO" })))
mmioNetwork.io.in.head <> coreplexIO.master.mmio.get
outer.legacy.module.io.legacy <> mmioNetwork.port("TL2")
pBus.io.in.head <> coreplexIO.master.mmio.get
outer.legacy.module.io.legacy <> pBus.port("TL2")
println("Generated Address Map")
for (entry <- p(GlobalAddrMap).flatten) {

4
src/main/scala/rocketchip/Periphery.scala
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@ -204,10 +204,10 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
implicit val p: Parameters
val outer: PeripheryMasterMMIO
val io: PeripheryMasterMMIOBundle
val mmioNetwork: TileLinkRecursiveInterconnect
val pBus: TileLinkRecursiveInterconnect
val mmio_ports = p(ExtMMIOPorts) map { port =>
TileLinkWidthAdapter(mmioNetwork.port(port.name), "MMIO_Outermost")
TileLinkWidthAdapter(pBus.port(port.name), "MMIO_Outermost")
}
val mmio_axi_start = 0

16
src/main/scala/rocketchip/Utils.scala
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@ -53,7 +53,7 @@ class GlobalVariable[T] {
object GenerateGlobalAddrMap {
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
lazy val intIOAddrMap: AddrMap = {
lazy val cBusIOAddrMap: AddrMap = {
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
@ -84,15 +84,15 @@ object GenerateGlobalAddrMap {
}.flatten
lazy val tl2AddrMap = new AddrMap(tl2Devices, collapse = true)
lazy val extIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
lazy val pBusIOAddrMap = new AddrMap(AddrMapEntry("TL2", tl2AddrMap) +: (p(ExtMMIOPorts) ++ pDevicesEntries), collapse = true)
val memBase = 0x80000000L
val memSize = p(ExtMemSize)
Dump("MEM_BASE", memBase)
val intern = AddrMapEntry("int", intIOAddrMap)
val extern = AddrMapEntry("ext", extIOAddrMap)
val io = AddrMapEntry("io", AddrMap((intern +: (!extIOAddrMap.isEmpty).option(extern).toSeq):_*))
val cBus = AddrMapEntry("cbus", cBusIOAddrMap)
val pBus = AddrMapEntry("pbus", pBusIOAddrMap)
val io = AddrMapEntry("io", AddrMap((cBus +: (!pBusIOAddrMap.isEmpty).option(pBus).toSeq):_*))
val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
AddrMap((io +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*)
}
@ -101,8 +101,8 @@ object GenerateGlobalAddrMap {
object GenerateConfigString {
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry], peripheryManagers: Seq[TLManagerParameters]) = {
val addrMap = p(GlobalAddrMap)
val plicAddr = addrMap("io:int:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:ext:TL2:clint").start)
val plicAddr = addrMap("io:cbus:plic").start
val clint = CoreplexLocalInterrupterConfig(0, addrMap("io:pbus:TL2:clint").start)
val xLen = p(XLen)
val res = new StringBuilder
res append "plic {\n"
@ -155,7 +155,7 @@ object GenerateConfigString {
}
res append "};\n"
pDevicesEntries foreach { entry =>
val region = addrMap("io:ext:" + entry.name)
val region = addrMap("io:pbus:" + entry.name)
res append s"${entry.name} {\n"
res append s" addr 0x${region.start.toString(16)};\n"
res append s" size 0x${region.size.toString(16)}; \n"