riscv/rocket-chip
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rename internal/external MMIO network to cbus/pbus respectively

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This commit is contained in:
Yunsup Lee
2016-09-21 18:16:04 -07:00
parent 3a809b209f
commit 5bb575ef74
8 changed files with 25 additions and 25 deletions
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2
src/main/scala/groundtest/Configs.scala
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@ -137,7 +137,7 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:ext:TL2:testram").map(name =>
targets = Seq("mem", "io:pbus:TL2:testram").map(name =>
site(GlobalAddrMap)(name).start.longValue),
width = 8,
operations = 1000,