riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

rename internal/external MMIO network to cbus/pbus respectively

Browse Source
This commit is contained in:
Yunsup Lee
2016-09-21 18:16:04 -07:00
parent 3a809b209f
commit 5bb575ef74
8 changed files with 25 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/groundtest/BusMasterTest.scala
View File

@ -69,7 +69,7 @@ class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
val state = Reg(init = s_idle)
val busMasterBlock = addrMap("io:ext:busmaster").start >> p(CacheBlockOffsetBits)
val busMasterBlock = addrMap("io:pbus:busmaster").start >> p(CacheBlockOffsetBits)
val start_acq = Put(
client_xact_id = UInt(0),
addr_block = UInt(busMasterBlock),

2
src/main/scala/groundtest/Configs.scala
View File

@ -137,7 +137,7 @@ class WithComparator extends Config(
case BuildGroundTest =>
(p: Parameters) => Module(new ComparatorCore()(p))
case ComparatorKey => ComparatorParameters(
targets = Seq("mem", "io:ext:TL2:testram").map(name =>
targets = Seq("mem", "io:pbus:TL2:testram").map(name =>
site(GlobalAddrMap)(name).start.longValue),
width = 8,
operations = 1000,

2
src/main/scala/groundtest/Regression.scala
View File

@ -72,7 +72,7 @@ class IOGetAfterPutBlockRegression(implicit p: Parameters) extends Regression()(
io.mem.grant.ready := Bool(true)
io.cache.req.valid := !get_sent && started
io.cache.req.bits.addr := UInt(addrMap("io:ext:TL2:bootrom").start)
io.cache.req.bits.addr := UInt(addrMap("io:pbus:TL2:bootrom").start)
io.cache.req.bits.typ := UInt(log2Ceil(32 / 8))
io.cache.req.bits.cmd := M_XRD
io.cache.req.bits.tag := UInt(0)