riscv/rocket-chip
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Plic: support 0 interrupts gracefully

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This commit is contained in:
Wesley W. Terpstra 2016-11-18 18:07:44 -08:00
parent 13ec3853ed
commit 5b594ced29
1 changed files with 1 additions and 1 deletions
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src/main/scala/uncore/devices/Plic.scala
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@ -135,7 +135,7 @@ class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC00000
val gateway = Module(new LevelGateway) val gateway = Module(new LevelGateway)
gateway.io.interrupt := i gateway.io.interrupt := i
gateway.io.plic gateway.io.plic
}) } ++ (if (interrupts.isEmpty) Some(Wire(new GatewayPLICIO)) else None))
val priority = val priority =
if (nPriorities > 0) Reg(Vec(nDevices+1, UInt(width=log2Up(nPriorities+1)))) if (nPriorities > 0) Reg(Vec(nDevices+1, UInt(width=log2Up(nPriorities+1))))