riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit

Browse Source
This commit is contained in:
Huy Vo
2012-02-26 17:24:08 -08:00
parent 69260756bd
commit 5b0f7ccf68
4 changed files with 20 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/icache.scala
View File

@ -94,7 +94,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
for (i <- 0 until assoc)
{
val repl_me = (repl_way === UFix(i))
val tag_array = Mem(lines, r_cpu_miss_tag);
val tag_array = Mem(lines){ Bits(width=tagmsb-taglsb+1) }
tag_array.setReadLatency(1);
tag_array.setTarget('inst);
val tag_rdata = tag_array.rw(tag_addr, r_cpu_miss_tag, tag_we && repl_me);
@ -112,7 +112,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component {
val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb))
// data array
val data_array = Mem(lines*REFILL_CYCLES, io.mem.resp_data);
val data_array = Mem(lines*REFILL_CYCLES){ Bits(width = MEM_DATA_BITS) }
data_array.setReadLatency(1);
data_array.setTarget('inst);
val data_out = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val && repl_me)