From 5b0f7ccf6889ebc04e8316652adacf676599cdd6 Mon Sep 17 00:00:00 2001 From: Huy Vo Date: Sun, 26 Feb 2012 17:24:08 -0800 Subject: [PATCH] updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit --- rocket/src/main/scala/coherence.scala | 25 ++++++++++++------------- rocket/src/main/scala/dpath_util.scala | 2 +- rocket/src/main/scala/icache.scala | 4 ++-- rocket/src/main/scala/nbdcache.scala | 10 +++++----- 4 files changed, 20 insertions(+), 21 deletions(-) diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala index d419dd52..af0d27c8 100644 --- a/rocket/src/main/scala/coherence.scala +++ b/rocket/src/main/scala/coherence.scala @@ -2,7 +2,6 @@ package rocket import Chisel._ import Constants._ -import hwacha.GenArray class HubMemReq extends Bundle { val rw = Bool() @@ -205,18 +204,18 @@ class CoherenceHubNoDir extends CoherenceHub { } val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_)) - val busy_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} } - val addr_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} } - val tile_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} } - val tile_xact_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} } - val t_type_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} } - val sh_count_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} } - val send_x_rep_ack_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} } + val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} } + val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} } + val tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} } + val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} } + val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} } + val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} } + val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} } - val do_free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} } - val p_rep_has_data_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} } - val p_rep_data_idx_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} } - val rep_cnt_dec_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} } + val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} } + val p_rep_has_data_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} } + val p_rep_data_idx_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} } + val rep_cnt_dec_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} } for( i <- 0 until NGLOBAL_XACTS) { busy_arr.write( UFix(i), trackerList(i).io.busy) @@ -243,7 +242,7 @@ class CoherenceHubNoDir extends CoherenceHub { val t = trackerList(i).io conflicts(i) := t.busy(i) && coherenceConflict(t.addr, init.bits.address) } - aborting(j) := (conflicts.orR || busy_arr.flatten().andR) + aborting(j) := (conflicts.orR || busy_arr.toBits().andR) abort.valid := init.valid && aborting abort.bits.tile_xact_id := init.bits.tile_xact_id init.ready := aborting(j) || initiating(j) diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index b36a5af8..269029f4 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -261,7 +261,7 @@ class rocketDpathRegfile extends Component { override val io = new ioRegfile(); - val regfile = Mem(32, io.w0.data); + val regfile = Mem(32){ Bits(width=64) } regfile.setReadLatency(0); regfile.setTarget('inst); regfile.write(io.w0.addr, io.w0.data, io.w0.en); diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index ca3c9219..2686b658 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -94,7 +94,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component { for (i <- 0 until assoc) { val repl_me = (repl_way === UFix(i)) - val tag_array = Mem(lines, r_cpu_miss_tag); + val tag_array = Mem(lines){ Bits(width=tagmsb-taglsb+1) } tag_array.setReadLatency(1); tag_array.setTarget('inst); val tag_rdata = tag_array.rw(tag_addr, r_cpu_miss_tag, tag_we && repl_me); @@ -112,7 +112,7 @@ class rocketICache(sets: Int, assoc: Int) extends Component { val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb)) // data array - val data_array = Mem(lines*REFILL_CYCLES, io.mem.resp_data); + val data_array = Mem(lines*REFILL_CYCLES){ Bits(width = MEM_DATA_BITS) } data_array.setReadLatency(1); data_array.setTarget('inst); val data_out = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val && repl_me) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 16b6fb63..08acdf01 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -391,7 +391,7 @@ class ReplayUnit extends Component { val sdq_wen = io.sdq_enq.valid && io.sdq_enq.ready val sdq_addr = Mux(sdq_ren_retry, rp.sdq_id, Mux(sdq_ren_new, io.replay.bits.sdq_id, sdq_alloc_id)) - val sdq = Mem(NSDQ, io.sdq_enq.bits) + val sdq = Mem(NSDQ){ Bits(width=CPU_DATA_BITS) } sdq.setReadLatency(1); sdq.setTarget('inst) val sdq_dout = sdq.rw(sdq_addr, io.sdq_enq.bits, sdq_wen, cs = sdq_ren || sdq_wen) @@ -522,7 +522,7 @@ class MetaDataArray(lines: Int) extends Component { val state_req = (new ioDecoupled) { new MetaArrayReq() } } - val permissions_array = Mem(lines, Bits(width = 2)) + val permissions_array = Mem(lines){ Bits(width = 2) } permissions_array.setReadLatency(1); permissions_array.write(io.state_req.bits.idx, io.state_req.bits.data.state, io.state_req.valid && io.state_req.bits.rw) val permissions_rdata1 = permissions_array.rw(io.req.bits.idx, io.req.bits.data.state, io.req.valid && io.req.bits.rw) @@ -531,7 +531,7 @@ class MetaDataArray(lines: Int) extends Component { // this could be eliminated if the read port were combinational. val permissions_conflict = io.state_req.valid && (io.req.bits.idx === io.state_req.bits.idx) - val tag_array = Mem(lines, io.resp.tag) + val tag_array = Mem(lines){ Bits(width=TAG_BITS) } tag_array.setReadLatency(1); tag_array.setTarget('inst) val tag_rdata = tag_array.rw(io.req.bits.idx, io.req.bits.data.tag, io.req.valid && io.req.bits.rw, cs = io.req.valid) @@ -580,7 +580,7 @@ class DataArray(lines: Int) extends Component { val wmask = FillInterleaved(8, io.req.bits.wmask) - val array = Mem(lines*REFILL_CYCLES, io.resp) + val array = Mem(lines*REFILL_CYCLES){ Bits(width=MEM_DATA_BITS) } array.setReadLatency(1); array.setTarget('inst) val addr = Cat(io.req.bits.idx, io.req.bits.offset) @@ -802,7 +802,7 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence { val tag_match = Cat(Bits(0),tag_match_arr:_*).orR val tag_hit = r_cpu_req_val && tag_match val tag_miss = r_cpu_req_val && !tag_match - val hit_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use GenArray + val hit_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), hit_way_oh, meta.io.way_en) val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), hit_way_oh, data.io.way_en) val meta_resp_mux = Mux1H(NWAYS, meta_resp_way_oh, meta.io.resp)