riscv/rocket-chip
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RegFieldDesc: fix the output produced for undescribed registers

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This commit is contained in:
Megan Wachs 2018-02-16 10:24:12 -08:00
parent cf7cd03d64
commit 5affd3bec2
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/tilelink/RegisterRouter.scala
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@ -88,7 +88,7 @@ case class TLRegisterNode(
val regDescs = mapping.flatMap { case (offset, seq) => val regDescs = mapping.flatMap { case (offset, seq) =>
var currentBitOffset = 0 var currentBitOffset = 0
seq.zipWithIndex.map { case (f, i) => { seq.zipWithIndex.map { case (f, i) => {
val tmp = (f.desc.map{ _.name}.getOrElse(s"unnamedRegField${i}") -> ( val tmp = (f.desc.map{ _.name}.getOrElse(s"unnamedRegField${offset.toHexString}_${currentBitOffset}") -> (
("byteOffset" -> s"0x${offset.toHexString}") ~ ("byteOffset" -> s"0x${offset.toHexString}") ~
("bitOffset" -> currentBitOffset) ~ ("bitOffset" -> currentBitOffset) ~
("bitWidth" -> f.width) ~ ("bitWidth" -> f.width) ~