riscv/rocket-chip
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support for multiple tilelink paramerterizations in same design

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This commit is contained in:
Henry Cook
2014-09-24 11:34:16 -07:00
committed by Yunsup Lee
parent e2ed81dcd2
commit 5a840c5520
3 changed files with 16 additions and 7 deletions
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6
src/main/scala/RocketChip.scala
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@ -42,9 +42,11 @@ class OuterMemorySystem extends Module with TopLevelParameters {
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
// Create a converter between TileLinkIO and MemIO
val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
val conv = Module(new MemIOUncachedTileLinkIOConverter(2),
{ case TLId => "outer" })
if(params(NBanks) > 1) {
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)))
val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)),
{ case TLId => "outer" })
arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {