diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala
index d87610f6..d1b412f0 100644
--- a/src/main/scala/PublicConfigs.scala
+++ b/src/main/scala/PublicConfigs.scala
@@ -87,10 +87,17 @@ class DefaultConfig extends ChiselConfig {
       case LNMasters => site(NBanks)
       case LNClients => site(NTiles)+1
       case LNEndpoints => site(LNMasters) + site(LNClients)
+      case TLId => "inner"
       case TLCoherence => site(Coherence)
       case TLAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
-      case TLMasterXactIdBits => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
-      case TLClientXactIdBits => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
+      case TLMasterXactIdBits => site(TLId) match {
+        case "inner" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
+        case "outer" => 1
+      }
+      case TLClientXactIdBits => site(TLId) match {
+        case "inner" => log2Up(site(NMSHRs))+log2Up(site(NTilePorts))
+        case "outer" => log2Up(site(NReleaseTransactors)+site(NAcquireTransactors))
+      }
       case TLDataBits => site(CacheBlockBytes)*8
       case TLWriteMaskBits => 6
       case TLWordAddrBits  => 3
@@ -113,9 +120,9 @@ class DefaultConfig extends ChiselConfig {
       }
       case BuildCoherenceMaster => (id: Int) => {
         if(site[Boolean]("USE_L2_CACHE")) { 
-          Module(new L2HellaCache(id), { case CacheName => "L2" })
+          Module(new L2HellaCache(id, "inner", "outer"), { case CacheName => "L2" })
         } else {
-          Module(new L2CoherenceAgent(id), { case CacheName => "L2" })
+          Module(new L2CoherenceAgent(id, "inner", "outer"), { case CacheName => "L2" })
         }
       }
       case Coherence => {
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 952afa44..d3d74197 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -42,9 +42,11 @@ class OuterMemorySystem extends Module with TopLevelParameters {
   masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
 
   // Create a converter between TileLinkIO and MemIO
-  val conv = Module(new MemIOUncachedTileLinkIOConverter(2))
+  val conv = Module(new MemIOUncachedTileLinkIOConverter(2), 
+                    { case TLId => "outer" })
   if(params(NBanks) > 1) {
-    val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)))
+    val arb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NBanks)),
+                    { case TLId => "outer" })
     arb.io.in zip masterEndpoints.map(_.io.outer) map { case (arb, cache) => arb <> cache }
     conv.io.uncached <> arb.io.out
   } else {
diff --git a/uncore b/uncore
index f32dd06f..f294eddb 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit f32dd06f089376ea8a31b00be7d8ecbd3d86747f
+Subproject commit f294eddb44b7455cfaf4d533da1056dc8b88086e