riscv/rocket-chip
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switch memory interconnect from AXI to TileLink

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This commit is contained in:
Howard Mao 2016-03-31 18:18:30 -07:00
parent 6d5c98da7d
commit 5a74a9b1e7
3 changed files with 22 additions and 14 deletions
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5
src/main/scala/Configs.scala
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@ -217,7 +217,10 @@ class DefaultConfig extends Config (
maxClientsPerPort = site(NAcquireTransactors) + 2, maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1, maxManagerXacts = 1,
dataBits = site(CacheBlockBytes)*8) dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats)) case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
maxClientXacts = site(NAcquireTransactors) + 2,
maxClientsPerPort = site(NBanksPerMemoryChannel),
dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => { case TLKey("L2toMMIO") => {
val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase)) val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
TileLinkParameters( TileLinkParameters(

29
src/main/scala/RocketChip.scala
View File

@ -278,11 +278,13 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
"More memory channels elaborated than can be enabled") "More memory channels elaborated than can be enabled")
val mem_ic = val mem_ic =
if (channelConfigs.size == 1) { if (channelConfigs.size == 1) {
val ic = Module(new NastiMemoryInterconnect(nBanksPerMemChannel, nMemChannels)) val ic = Module(new TileLinkMemoryInterconnect(
nBanksPerMemChannel, nMemChannels)(outermostTLParams))
ic ic
} else { } else {
val nBanks = nBanksPerMemChannel * nMemChannels val nBanks = nBanksPerMemChannel * nMemChannels
val ic = Module(new NastiMemorySelector(nBanks, nMemChannels, channelConfigs)) val ic = Module(new TileLinkMemorySelector(
nBanks, nMemChannels, channelConfigs)(outermostTLParams))
ic.io.select := io.memory_channel_mux_select ic.io.select := io.memory_channel_mux_select
ic ic
} }
@ -290,11 +292,9 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
for ((bank, i) <- managerEndpoints.zipWithIndex) { for ((bank, i) <- managerEndpoints.zipWithIndex) {
val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams)) val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost")) val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams) unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
narrow.io.in <> unwrap.io.out narrow.io.in <> unwrap.io.out
conv.io.tl <> narrow.io.out mem_ic.io.in(i) <> narrow.io.out
TopUtils.connectNasti(mem_ic.io.masters(i), conv.io.nasti)
} }
val mmioOutermostTLParams = p.alterPartial({case TLId => "MMIO_Outermost"}) val mmioOutermostTLParams = p.alterPartial({case TLId => "MMIO_Outermost"})
@ -307,8 +307,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
mmio_narrow.io.in <> mmioManager.io.outer mmio_narrow.io.in <> mmioManager.io.outer
mmio_net.io.in.head <> mmio_narrow.io.out mmio_net.io.in.head <> mmio_narrow.io.out
def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO) = { def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
val conv = Module(new NastiIOTileLinkIOConverter()(mmioOutermostTLParams)) val conv = Module(new NastiIOTileLinkIOConverter())
conv.io.tl <> tl conv.io.tl <> tl
TopUtils.connectNasti(nasti, conv.io.nasti) TopUtils.connectNasti(nasti, conv.io.nasti)
} }
@ -317,13 +317,13 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val csrName = s"conf:csr$i" val csrName = s"conf:csr$i"
val csrPort = addrHashMap(csrName).port val csrPort = addrHashMap(csrName).port
val conv = Module(new SmiIONastiIOConverter(xLen, csrAddrBits)) val conv = Module(new SmiIONastiIOConverter(xLen, csrAddrBits))
connectTilelinkNasti(conv.io.nasti, mmio_net.io.out(csrPort)) connectTilelinkNasti(conv.io.nasti, mmio_net.io.out(csrPort))(mmioOutermostTLParams)
io.csr(i) <> conv.io.smi io.csr(i) <> conv.io.smi
} }
val scrPort = addrHashMap("conf:scr").port val scrPort = addrHashMap("conf:scr").port
val scr_conv = Module(new SmiIONastiIOConverter(scrDataBits, scrAddrBits)) val scr_conv = Module(new SmiIONastiIOConverter(scrDataBits, scrAddrBits))
connectTilelinkNasti(scr_conv.io.nasti, mmio_net.io.out(scrPort)) connectTilelinkNasti(scr_conv.io.nasti, mmio_net.io.out(scrPort))(mmioOutermostTLParams)
io.scr <> scr_conv.io.smi io.scr <> scr_conv.io.smi
if (p(UseStreamLoopback)) { if (p(UseStreamLoopback)) {
@ -331,14 +331,19 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val lo_size = p(StreamLoopbackSize) val lo_size = p(StreamLoopbackSize)
val lo_conv = Module(new NastiIOStreamIOConverter(lo_width)) val lo_conv = Module(new NastiIOStreamIOConverter(lo_width))
val lo_port = addrHashMap("devices:loopback").port val lo_port = addrHashMap("devices:loopback").port
connectTilelinkNasti(lo_conv.io.nasti, mmio_net.io.out(lo_port)) connectTilelinkNasti(lo_conv.io.nasti, mmio_net.io.out(lo_port))(mmioOutermostTLParams)
lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size) lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
} }
val dtPort = addrHashMap("conf:devicetree").port val dtPort = addrHashMap("conf:devicetree").port
connectTilelinkNasti(io.deviceTree, mmio_net.io.out(dtPort)) connectTilelinkNasti(io.deviceTree, mmio_net.io.out(dtPort))(mmioOutermostTLParams)
val mem_channels = Wire(Vec(nMemChannels, new NastiIO))
mem_channels.zip(mem_ic.io.out).foreach { case (ch, out) =>
connectTilelinkNasti(ch, out)(outermostTLParams)
}
val mem_channels = mem_ic.io.slaves
// Create a SerDes for backup memory port // Create a SerDes for backup memory port
if(p(UseBackupMemoryPort)) { if(p(UseBackupMemoryPort)) {
VLSIUtils.doOuterMemorySystemSerdes( VLSIUtils.doOuterMemorySystemSerdes(

2
uncore

@ -1 +1 @@
Subproject commit 7206757629076fd75df42f90a23637b88f652095 Subproject commit ae219e32b045abefe8b957d8c7f10ce445804fbc