From 5a74a9b1e738c8a26efb9f25330e9b6ce9fec186 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Thu, 31 Mar 2016 18:18:30 -0700
Subject: [PATCH] switch memory interconnect from AXI to TileLink

---
 src/main/scala/Configs.scala    |  5 ++++-
 src/main/scala/RocketChip.scala | 29 +++++++++++++++++------------
 uncore                          |  2 +-
 3 files changed, 22 insertions(+), 14 deletions(-)

diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 05dd7b92..f54d5f83 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -217,7 +217,10 @@ class DefaultConfig extends Config (
           maxClientsPerPort = site(NAcquireTransactors) + 2,
           maxManagerXacts = 1,
           dataBits = site(CacheBlockBytes)*8)
-      case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
+      case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
+        maxClientXacts = site(NAcquireTransactors) + 2,
+        maxClientsPerPort = site(NBanksPerMemoryChannel),
+        dataBeats = site(MIFDataBeats))
       case TLKey("L2toMMIO") => {
         val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
         TileLinkParameters(
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 0a37d26f..dd143165 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -278,11 +278,13 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
                 "More memory channels elaborated than can be enabled")
   val mem_ic =
     if (channelConfigs.size == 1) {
-      val ic = Module(new NastiMemoryInterconnect(nBanksPerMemChannel, nMemChannels))
+      val ic = Module(new TileLinkMemoryInterconnect(
+        nBanksPerMemChannel, nMemChannels)(outermostTLParams))
       ic
     } else {
       val nBanks = nBanksPerMemChannel * nMemChannels
-      val ic = Module(new NastiMemorySelector(nBanks, nMemChannels, channelConfigs))
+      val ic = Module(new TileLinkMemorySelector(
+        nBanks, nMemChannels, channelConfigs)(outermostTLParams))
       ic.io.select := io.memory_channel_mux_select
       ic
     }
@@ -290,11 +292,9 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
   for ((bank, i) <- managerEndpoints.zipWithIndex) {
     val unwrap = Module(new ClientTileLinkIOUnwrapper()(outerTLParams))
     val narrow = Module(new TileLinkIONarrower("L2toMC", "Outermost"))
-    val conv = Module(new NastiIOTileLinkIOConverter()(outermostTLParams))
     unwrap.io.in <> ClientTileLinkEnqueuer(bank.outerTL, backendBuffering)(outerTLParams)
     narrow.io.in <> unwrap.io.out
-    conv.io.tl <> narrow.io.out
-    TopUtils.connectNasti(mem_ic.io.masters(i), conv.io.nasti)
+    mem_ic.io.in(i) <> narrow.io.out
   }
 
   val mmioOutermostTLParams = p.alterPartial({case TLId => "MMIO_Outermost"})
@@ -307,8 +307,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
   mmio_narrow.io.in <> mmioManager.io.outer
   mmio_net.io.in.head <> mmio_narrow.io.out
 
-  def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO) = {
-    val conv = Module(new NastiIOTileLinkIOConverter()(mmioOutermostTLParams))
+  def connectTilelinkNasti(nasti: NastiIO, tl: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
+    val conv = Module(new NastiIOTileLinkIOConverter())
     conv.io.tl <> tl
     TopUtils.connectNasti(nasti, conv.io.nasti)
   }
@@ -317,13 +317,13 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     val csrName = s"conf:csr$i"
     val csrPort = addrHashMap(csrName).port
     val conv = Module(new SmiIONastiIOConverter(xLen, csrAddrBits))
-    connectTilelinkNasti(conv.io.nasti, mmio_net.io.out(csrPort))
+    connectTilelinkNasti(conv.io.nasti, mmio_net.io.out(csrPort))(mmioOutermostTLParams)
     io.csr(i) <> conv.io.smi
   }
 
   val scrPort = addrHashMap("conf:scr").port
   val scr_conv = Module(new SmiIONastiIOConverter(scrDataBits, scrAddrBits))
-  connectTilelinkNasti(scr_conv.io.nasti, mmio_net.io.out(scrPort))
+  connectTilelinkNasti(scr_conv.io.nasti, mmio_net.io.out(scrPort))(mmioOutermostTLParams)
   io.scr <> scr_conv.io.smi
 
   if (p(UseStreamLoopback)) {
@@ -331,14 +331,19 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     val lo_size = p(StreamLoopbackSize)
     val lo_conv = Module(new NastiIOStreamIOConverter(lo_width))
     val lo_port = addrHashMap("devices:loopback").port
-    connectTilelinkNasti(lo_conv.io.nasti, mmio_net.io.out(lo_port))
+    connectTilelinkNasti(lo_conv.io.nasti, mmio_net.io.out(lo_port))(mmioOutermostTLParams)
     lo_conv.io.stream.in <> Queue(lo_conv.io.stream.out, lo_size)
   }
 
   val dtPort = addrHashMap("conf:devicetree").port
-  connectTilelinkNasti(io.deviceTree, mmio_net.io.out(dtPort))
+  connectTilelinkNasti(io.deviceTree, mmio_net.io.out(dtPort))(mmioOutermostTLParams)
+
+  val mem_channels = Wire(Vec(nMemChannels, new NastiIO))
+
+  mem_channels.zip(mem_ic.io.out).foreach { case (ch, out) =>
+    connectTilelinkNasti(ch, out)(outermostTLParams)
+  }
 
-  val mem_channels = mem_ic.io.slaves
   // Create a SerDes for backup memory port
   if(p(UseBackupMemoryPort)) {
     VLSIUtils.doOuterMemorySystemSerdes(
diff --git a/uncore b/uncore
index 72067576..ae219e32 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 7206757629076fd75df42f90a23637b88f652095
+Subproject commit ae219e32b045abefe8b957d8c7f10ce445804fbc