riscv/rocket-chip
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switch memory interconnect from AXI to TileLink

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This commit is contained in:
Howard Mao
2016-03-31 18:18:30 -07:00
parent 6d5c98da7d
commit 5a74a9b1e7
3 changed files with 22 additions and 14 deletions
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5
src/main/scala/Configs.scala
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@ -217,7 +217,10 @@ class DefaultConfig extends Config (
maxClientsPerPort = site(NAcquireTransactors) + 2,
maxManagerXacts = 1,
dataBits = site(CacheBlockBytes)*8)
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(dataBeats = site(MIFDataBeats))
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
maxClientXacts = site(NAcquireTransactors) + 2,
maxClientsPerPort = site(NBanksPerMemoryChannel),
dataBeats = site(MIFDataBeats))
case TLKey("L2toMMIO") => {
val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase))
TileLinkParameters(