riscv/rocket-chip
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mideleg/medeleg not present without less-privileged traps

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This commit is contained in:
Andrew Waterman 2017-03-20 05:47:35 -07:00
parent 38808f55d5
commit 59d6afa132
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/CSR.scala
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@ -325,8 +325,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
CSRs.mtvec -> reg_mtvec,
CSRs.mip -> read_mip,
CSRs.mie -> reg_mie,
CSRs.mideleg -> reg_mideleg,
CSRs.medeleg -> reg_medeleg,
CSRs.mscratch -> reg_mscratch,
CSRs.mepc -> reg_mepc.sextTo(xLen),
CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen),
@ -385,6 +383,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
read_mapping += CSRs.sepc -> reg_sepc.sextTo(xLen)
read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen)
read_mapping += CSRs.scounteren -> reg_scounteren
read_mapping += CSRs.mideleg -> reg_mideleg
read_mapping += CSRs.medeleg -> reg_medeleg
}
if (usingUser) {