From 59d6afa132a496b0f21b6507836aef0459f13176 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 20 Mar 2017 05:47:35 -0700 Subject: [PATCH] mideleg/medeleg not present without less-privileged traps --- src/main/scala/rocket/CSR.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 6514eec3..91311f5c 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -325,8 +325,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param CSRs.mtvec -> reg_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, - CSRs.mideleg -> reg_mideleg, - CSRs.medeleg -> reg_medeleg, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> reg_mepc.sextTo(xLen), CSRs.mbadaddr -> reg_mbadaddr.sextTo(xLen), @@ -385,6 +383,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param read_mapping += CSRs.sepc -> reg_sepc.sextTo(xLen) read_mapping += CSRs.stvec -> reg_stvec.sextTo(xLen) read_mapping += CSRs.scounteren -> reg_scounteren + read_mapping += CSRs.mideleg -> reg_mideleg + read_mapping += CSRs.medeleg -> reg_medeleg } if (usingUser) {