diplomacy: move manager unification to meta-data only
Now that PMA circuits already perform address unification, there is no QoR gained by throwing away the true and complete diplomatic address+node information. Defer the unification to pretty printing the DTS address map only.
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@ -82,8 +82,10 @@ trait CoreplexNetwork extends HasCoreplexParameters {
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}
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}
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// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
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lazy val topManagers = Some(ManagerUnification(l1tol2.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil)))
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ResourceBinding {
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val managers = l1tol2.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil)
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val managers = topManagers.get
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val max = managers.flatMap(_.address).map(_.max).max
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val width = ResourceInt((log2Ceil(max)+31) / 32)
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Resource(root, "width").bind(width)
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@ -113,7 +115,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
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val io: CoreplexNetworkBundle
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println("Generated Address Map")
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val ranges = outer.l1tol2.node.edgesIn(0).manager.managers.flatMap { manager =>
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val ranges = outer.topManagers.get.flatMap { manager =>
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val prot = (if (manager.supportsGet) "R" else "") +
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(if (manager.supportsPutFull) "W" else "") +
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(if (manager.executable) "X" else "") +
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@ -57,14 +57,14 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
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seq(0).copy(
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minLatency = seq.map(_.minLatency).min,
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endSinkId = outputIdRanges.map(_.map(_.end).getOrElse(0)).max,
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managers = ManagerUnification(seq.flatMap { port =>
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managers = seq.flatMap { port =>
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require (port.beatBytes == seq(0).beatBytes,
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s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
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val fifoIdMapper = fifoIdFactory()
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port.managers map { manager => manager.copy(
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fifoId = manager.fifoId.map(fifoIdMapper(_))
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)}
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})
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}
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)
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})
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