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diplomacy: move manager unification to meta-data only

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Now that PMA circuits already perform address unification, there is
no QoR gained by throwing away the true and complete diplomatic
address+node information. Defer the unification to pretty printing
the DTS address map only.
This commit is contained in:
Wesley W. Terpstra
2017-06-01 15:16:01 -07:00
parent 0fe625c52f
commit 5994714970
2 changed files with 6 additions and 4 deletions
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6
src/main/scala/coreplex/CoreplexNetwork.scala
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@@ -82,8 +82,10 @@ trait CoreplexNetwork extends HasCoreplexParameters {
} }
} }
// Make topManagers an Option[] so as to avoid LM name reflection evaluating it...
lazy val topManagers = Some(ManagerUnification(l1tol2.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil)))
ResourceBinding { ResourceBinding {
val managers = l1tol2.node.edgesIn.headOption.map(_.manager.managers).getOrElse(Nil) val managers = topManagers.get
val max = managers.flatMap(_.address).map(_.max).max val max = managers.flatMap(_.address).map(_.max).max
val width = ResourceInt((log2Ceil(max)+31) / 32) val width = ResourceInt((log2Ceil(max)+31) / 32)
Resource(root, "width").bind(width) Resource(root, "width").bind(width)
@@ -113,7 +115,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
val io: CoreplexNetworkBundle val io: CoreplexNetworkBundle
println("Generated Address Map") println("Generated Address Map")
val ranges = outer.l1tol2.node.edgesIn(0).manager.managers.flatMap { manager => val ranges = outer.topManagers.get.flatMap { manager =>
val prot = (if (manager.supportsGet) "R" else "") + val prot = (if (manager.supportsGet) "R" else "") +
(if (manager.supportsPutFull) "W" else "") + (if (manager.supportsPutFull) "W" else "") +
(if (manager.executable) "X" else "") + (if (manager.executable) "X" else "") +

4
src/main/scala/uncore/tilelink2/Xbar.scala
View File

@@ -57,14 +57,14 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
seq(0).copy( seq(0).copy(
minLatency = seq.map(_.minLatency).min, minLatency = seq.map(_.minLatency).min,
endSinkId = outputIdRanges.map(_.map(_.end).getOrElse(0)).max, endSinkId = outputIdRanges.map(_.map(_.end).getOrElse(0)).max,
managers = ManagerUnification(seq.flatMap { port => managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes, require (port.beatBytes == seq(0).beatBytes,
s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") s"Xbar data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory() val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.copy( port.managers map { manager => manager.copy(
fifoId = manager.fifoId.map(fifoIdMapper(_)) fifoId = manager.fifoId.map(fifoIdMapper(_))
)} )}
}) }
) )
}) })