riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

debug: Clean up ValidReg assertion.

Browse Source
This commit is contained in:
Megan Wachs 2017-04-19 13:56:47 -07:00
parent 0c013a56c0
commit 5934779082
1 changed files with 12 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/main/scala/rocketchip/DebugTransport.scala
View File

@ -196,26 +196,31 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
//--------------------------------------------------------
// Drive Ready Valid Interface
assert(!(dmiAccessChain.io.update.valid && io.dmi.req.ready), "Conflicting updates for dmiReqValid, should not happen.");
val dmiReqValidCheck = Wire(init = Bool(false))
assert(!(dmiReqValidCheck && io.dmi.req.fire()), "Conflicting updates for dmiReqValidReg, should not happen.");
when (dmiAccessChain.io.update.valid) {
when (skipOpReg) {
// Do Nothing
}.elsewhen(downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
// Do Nothing
} .elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
//Do Nothing
dmiReqReg.addr := UInt(0)
dmiReqReg.data := UInt(0)
dmiReqReg.op := UInt(0)
}.otherwise {
dmiReqReg := dmiAccessChain.io.update.bits
dmiReqValidReg := Bool(true)
}
}.otherwise {
when (io.dmi.req.ready) {
dmiReqValidReg := Bool(false)
dmiReqValidCheck := Bool(true)
}
}
when (io.dmi.req.fire()) {
dmiReqValidReg := Bool(false)
}
io.dmi.resp.ready := dmiAccessChain.io.capture.capture
io.dmi.req.valid := dmiReqValidReg