From 5934779082642e53fc1cb52ae628261d805dc05b Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 19 Apr 2017 13:56:47 -0700
Subject: [PATCH] debug: Clean up ValidReg assertion.

---
 .../scala/rocketchip/DebugTransport.scala     | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/rocketchip/DebugTransport.scala b/src/main/scala/rocketchip/DebugTransport.scala
index 3dc81e5b..4cebca2e 100644
--- a/src/main/scala/rocketchip/DebugTransport.scala
+++ b/src/main/scala/rocketchip/DebugTransport.scala
@@ -196,26 +196,31 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
   //--------------------------------------------------------
   // Drive Ready Valid Interface
 
-  assert(!(dmiAccessChain.io.update.valid && io.dmi.req.ready), "Conflicting updates for dmiReqValid, should not happen.");
+  val dmiReqValidCheck = Wire(init = Bool(false))
+  assert(!(dmiReqValidCheck && io.dmi.req.fire()), "Conflicting updates for dmiReqValidReg, should not happen.");
 
   when (dmiAccessChain.io.update.valid) {
     when (skipOpReg) {
       // Do Nothing
-    }.elsewhen(downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
-      // Do Nothing
+    } .elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
+      //Do Nothing
       dmiReqReg.addr := UInt(0)
       dmiReqReg.data := UInt(0)
       dmiReqReg.op   := UInt(0)
+
     }.otherwise {
       dmiReqReg := dmiAccessChain.io.update.bits
       dmiReqValidReg := Bool(true)
-    }
-  }.otherwise {
-    when (io.dmi.req.ready) {
-      dmiReqValidReg := Bool(false)
+      dmiReqValidCheck := Bool(true)
     }
   }
 
+  when (io.dmi.req.fire()) {
+    dmiReqValidReg := Bool(false)
+  }
+
+  
+
   io.dmi.resp.ready := dmiAccessChain.io.capture.capture
   io.dmi.req.valid := dmiReqValidReg