riscv/rocket-chip
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debug: Clean up ValidReg assertion.

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This commit is contained in:
Megan Wachs 2017-04-19 13:56:47 -07:00
parent 0c013a56c0
commit 5934779082
1 changed files with 12 additions and 7 deletions
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19
src/main/scala/rocketchip/DebugTransport.scala
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@ -196,26 +196,31 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
//-------------------------------------------------------- //--------------------------------------------------------
// Drive Ready Valid Interface // Drive Ready Valid Interface
assert(!(dmiAccessChain.io.update.valid && io.dmi.req.ready), "Conflicting updates for dmiReqValid, should not happen."); val dmiReqValidCheck = Wire(init = Bool(false))
assert(!(dmiReqValidCheck && io.dmi.req.fire()), "Conflicting updates for dmiReqValidReg, should not happen.");
when (dmiAccessChain.io.update.valid) { when (dmiAccessChain.io.update.valid) {
when (skipOpReg) { when (skipOpReg) {
// Do Nothing // Do Nothing
}.elsewhen(downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) { } .elsewhen (downgradeOpReg || (dmiAccessChain.io.update.bits.op === DMIConsts.dmi_OP_NONE)) {
// Do Nothing //Do Nothing
dmiReqReg.addr := UInt(0) dmiReqReg.addr := UInt(0)
dmiReqReg.data := UInt(0) dmiReqReg.data := UInt(0)
dmiReqReg.op := UInt(0) dmiReqReg.op := UInt(0)
}.otherwise { }.otherwise {
dmiReqReg := dmiAccessChain.io.update.bits dmiReqReg := dmiAccessChain.io.update.bits
dmiReqValidReg := Bool(true) dmiReqValidReg := Bool(true)
} dmiReqValidCheck := Bool(true)
}.otherwise {
when (io.dmi.req.ready) {
dmiReqValidReg := Bool(false)
} }
} }
when (io.dmi.req.fire()) {
dmiReqValidReg := Bool(false)
}
io.dmi.resp.ready := dmiAccessChain.io.capture.capture io.dmi.resp.ready := dmiAccessChain.io.capture.capture
io.dmi.req.valid := dmiReqValidReg io.dmi.req.valid := dmiReqValidReg