riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Get rid of useless mux

Browse Source
This commit is contained in:
Andrew Waterman 2016-01-28 11:44:59 -08:00
parent d170fcd913
commit 58fcc6b7c6
1 changed files with 1 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
rocket/src/main/scala/icache.scala
View File

@ -121,10 +121,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara
else data_array.write(s1_idx, e_d) else data_array.write(s1_idx, e_d)
} }
val s0_raddr = s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0)) val s0_raddr = s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0))
val s1_rdata = data_array.read(s0_raddr, !wen && s0_valid) s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid)
// if s1_tag_match is critical, replace with partial tag check
s1_dout(i) := 0
when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s1_dout(i) := s1_rdata }
} }
// output signals // output signals