From 58fcc6b7c6dcd7332d5be9c839b1ecdf97ce517a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 28 Jan 2016 11:44:59 -0800 Subject: [PATCH] Get rid of useless mux --- rocket/src/main/scala/icache.scala | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index ca68a2b7..2e6a5b17 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -121,10 +121,7 @@ class ICache(implicit p: Parameters) extends CoreModule()(p) with HasL1CachePara else data_array.write(s1_idx, e_d) } val s0_raddr = s0_pgoff(untagBits-1,blockOffBits-(if(refillCycles > 1) refill_cnt.getWidth else 0)) - val s1_rdata = data_array.read(s0_raddr, !wen && s0_valid) - // if s1_tag_match is critical, replace with partial tag check - s1_dout(i) := 0 - when (s1_valid && rdy && !stall && (Bool(isDM) || s1_tag_match(i))) { s1_dout(i) := s1_rdata } + s1_dout(i) := data_array.read(s0_raddr, !wen && s0_valid) } // output signals