riscv/rocket-chip
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Fix D$ for set size > page size

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This commit is contained in:
Andrew Waterman 2016-06-09 13:02:28 -07:00
parent dca55a2b35
commit 586c1079d0
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/dcache.scala
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@ -71,7 +71,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val s1_req = Reg(io.cpu.req.bits) val s1_req = Reg(io.cpu.req.bits)
when (metaReadArb.io.out.valid) { when (metaReadArb.io.out.valid) {
s1_req := io.cpu.req.bits s1_req := io.cpu.req.bits
s1_req.addr := Cat(io.cpu.req.bits.addr >> pgIdxBits, metaReadArb.io.out.bits.idx, io.cpu.req.bits.addr(blockOffBits-1,0)) s1_req.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaReadArb.io.out.bits.idx, io.cpu.req.bits.addr(blockOffBits-1,0))
} }
val s1_read = isRead(s1_req.cmd) val s1_read = isRead(s1_req.cmd)
val s1_write = isWrite(s1_req.cmd) val s1_write = isWrite(s1_req.cmd)