riscv/rocket-chip
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PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0

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This commit is contained in:
Wesley W. Terpstra 2017-03-03 00:28:55 -08:00
parent 46369850cf
commit 57a329408c
1 changed files with 6 additions and 4 deletions
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6
src/main/scala/rocketchip/Periphery.scala
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@ -59,11 +59,13 @@ trait PeripheryExtInterrupts {
val nExtInterrupts = p(NExtTopInterrupts) val nExtInterrupts = p(NExtTopInterrupts)
val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int)) val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
val extInterruptXing = LazyModule(new IntXing)
if (nExtInterrupts > 0) {
val extInterruptXing = LazyModule(new IntXing)
intBus.intnode := extInterruptXing.intnode intBus.intnode := extInterruptXing.intnode
extInterruptXing.intnode := extInterrupts extInterruptXing.intnode := extInterrupts
} }
}
trait PeripheryExtInterruptsBundle { trait PeripheryExtInterruptsBundle {
this: HasTopLevelNetworksBundle { this: HasTopLevelNetworksBundle {
@ -77,7 +79,7 @@ trait PeripheryExtInterruptsModule {
val outer: PeripheryExtInterrupts val outer: PeripheryExtInterrupts
val io: PeripheryExtInterruptsBundle val io: PeripheryExtInterruptsBundle
} => } =>
outer.extInterrupts.bundleIn(0).zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) } outer.extInterrupts.bundleIn.flatten.zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) }
} }
///// /////