From 57a329408c974e9f29b1652262be66ca42e7608c Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Fri, 3 Mar 2017 00:28:55 -0800
Subject: [PATCH] PeripheryExtInterrupts: elide node if NExtTopInterrupts = 0

---
 src/main/scala/rocketchip/Periphery.scala | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 3fdc8a41..65b59033 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -59,10 +59,12 @@ trait PeripheryExtInterrupts {
 
   val nExtInterrupts = p(NExtTopInterrupts)
   val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
-  val extInterruptXing = LazyModule(new IntXing)
 
-  intBus.intnode := extInterruptXing.intnode
-  extInterruptXing.intnode := extInterrupts
+  if (nExtInterrupts > 0) {
+    val extInterruptXing = LazyModule(new IntXing)
+    intBus.intnode := extInterruptXing.intnode
+    extInterruptXing.intnode := extInterrupts
+  }
 }
 
 trait PeripheryExtInterruptsBundle {
@@ -77,7 +79,7 @@ trait PeripheryExtInterruptsModule {
     val outer: PeripheryExtInterrupts
     val io: PeripheryExtInterruptsBundle
   } =>
-  outer.extInterrupts.bundleIn(0).zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) }
+  outer.extInterrupts.bundleIn.flatten.zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) }
 }
 
 /////