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Chisel3 compatibility potpourri

This commit is contained in:
Andrew Waterman 2015-07-30 23:52:42 -07:00
parent db7258f887
commit 57930e8a26
5 changed files with 5 additions and 5 deletions

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@ -306,7 +306,7 @@ class CSRFile extends CoreModule
reg_mstatus.prv2 := reg_mstatus.prv1 reg_mstatus.prv2 := reg_mstatus.prv1
reg_mstatus.ie2 := reg_mstatus.ie1 reg_mstatus.ie2 := reg_mstatus.ie1
reg_mepc := io.pc & SInt(-coreInstBytes) reg_mepc := ~(~io.pc | (coreInstBytes-1))
reg_mcause := io.cause reg_mcause := io.cause
when (csr_xcpt) { when (csr_xcpt) {
reg_mcause := Causes.illegal_instruction reg_mcause := Causes.illegal_instruction

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@ -439,7 +439,7 @@ class FPU extends Module
val divSqrt_in_flight = Reg(init=Bool(false)) val divSqrt_in_flight = Reg(init=Bool(false))
// writeback arbitration // writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: Bits, wexc: Bits) case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: UInt, wexc: UInt)
val pipes = List( val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc), Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc),

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@ -50,7 +50,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
val tlb = Module(new TLB) val tlb = Module(new TLB)
val s1_pc_ = Reg(UInt()) val s1_pc_ = Reg(UInt())
val s1_pc = s1_pc_ & SInt(-coreInstBytes) // discard PC LSBS (this propagates down the pipeline) val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
val s1_same_block = Reg(Bool()) val s1_same_block = Reg(Bool())
val s2_valid = Reg(init=Bool(true)) val s2_valid = Reg(init=Bool(true))
val s2_pc = Reg(init=UInt(START_ADDR)) val s2_pc = Reg(init=UInt(START_ADDR))

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@ -85,7 +85,7 @@ class PTW(n: Int) extends CoreModule
val (pte_cache_hit, pte_cache_data) = { val (pte_cache_hit, pte_cache_data) = {
val size = log2Up(pgLevels * 2) val size = log2Up(pgLevels * 2)
val plru = new PseudoLRU(size) val plru = new PseudoLRU(size)
val valid = Reg(init=Vec(Bool(), size)) val valid = Reg(Vec(Bool(), size))
val validBits = valid.toBits val validBits = valid.toBits
val tags = Mem(UInt(width = paddrBits), size) val tags = Mem(UInt(width = paddrBits), size)
val data = Mem(UInt(width = ppnBits), size) val data = Mem(UInt(width = ppnBits), size)

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@ -158,7 +158,7 @@ class TLB extends TLBModule {
val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm
val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1) val bad_va = io.req.bits.vpn(vpnBits) != io.req.bits.vpn(vpnBits-1)
// it's only a store hit if the dirty bit is set // it's only a store hit if the dirty bit is set
val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~(io.req.bits.store.toSInt & w_array)) val tag_hits = tag_cam.io.hits & (dirty_array.toBits | ~Mux(io.req.bits.store, w_array, UInt(0)))
val tag_hit = tag_hits.orR val tag_hit = tag_hits.orR
val tlb_hit = vm_enabled && tag_hit val tlb_hit = vm_enabled && tag_hit
val tlb_miss = vm_enabled && !tag_hit && !bad_va val tlb_miss = vm_enabled && !tag_hit && !bad_va