riscv/rocket-chip
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Chisel3 compatibility potpourri

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This commit is contained in:
Andrew Waterman
2015-07-30 23:52:42 -07:00
parent db7258f887
commit 57930e8a26
5 changed files with 5 additions and 5 deletions
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rocket/src/main/scala/icache.scala
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@@ -50,7 +50,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
val tlb = Module(new TLB)
val s1_pc_ = Reg(UInt())
val s1_pc = s1_pc_ & SInt(-coreInstBytes) // discard PC LSBS (this propagates down the pipeline)
val s1_pc = ~(~s1_pc_ | (coreInstBytes-1)) // discard PC LSBS (this propagates down the pipeline)
val s1_same_block = Reg(Bool())
val s2_valid = Reg(init=Bool(true))
val s2_pc = Reg(init=UInt(START_ADDR))