riscv/rocket-chip
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Chisel3 compatibility potpourri

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This commit is contained in:
Andrew Waterman
2015-07-30 23:52:42 -07:00
parent db7258f887
commit 57930e8a26
5 changed files with 5 additions and 5 deletions
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2
rocket/src/main/scala/fpu.scala
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@ -439,7 +439,7 @@ class FPU extends Module
val divSqrt_in_flight = Reg(init=Bool(false))
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: Bits, wexc: Bits)
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, wdata: UInt, wexc: UInt)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits.data, fpmu.io.out.bits.exc),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits.data, ifpu.io.out.bits.exc),